1. Field of the Invention
The present invention relates to data processing systems, and more particularly, to bridge systems including mechanisms for transferring information between buses.
2. Description of Related Art
Computers can use buses to transfer data between a host processor and various devices, such as memory devices and input/output devices. As used herein an xe2x80x9cinput/outputxe2x80x9d device is a device that either generates an input or receives an output (or does both). Thus xe2x80x9cinput/outputxe2x80x9d is used in the disjunctive. These buses may be arranged in a hierarchy with the host processor connected to a high level bus reserved for exchanging the data most urgently needed by the processor. Lower level buses may connect to devices having a lower priority.
Other reasons exist for providing separate buses. Placing an excessive number of devices on one bus produces high loading. Such loading makes a bus difficult to drive because of the power needed and the delays caused by signaling so many devices. Also, some devices on a bus may periodically act as a master and request control over a bus in order to communicate with a slave device. By segregating some devices on a separate bus, master devices can communicate with other devices on the lower level bus without tying up the bus used by the host processor or other masters.
The PCI bus standard is specified by the PCI Special Interest Group of Hillsboro, OR. The PCI bus features a 32-bit wide, multiplexed address-data (AD) Maintaining a high data throughput rate (e.g., a 33 MHZ clock rate) on the PCI bus leads to a fixed limitation on the number of electrical AC and DC loads on the bus. Speed considerations also limit the physical length of the bus and the capacitance that can be placed on the bus by the loads, while future PCI bus rates (e.g., 66 MHZ) will exacerbate the electrical load and capacitance concerns. Failure to observe these load restrictions can cause propagation delays and unsynchronized operation between bus devices.
To circumvent these loading restrictions, the PCI bus standard specifies a bridge to allow a primary PCI bus to communicate with a secondary PCI bus through such a bridge. Additional loads may be placed on the secondary bus without increasing the loading on the primary bus. For bridges of various types see U.S. Pat. Nos. 5,548,730 and 5,694,556.
The PCI bridge observes a hierarchy that allows an initiator or bus master on either bus to complete a transaction with a target on the other bus. As used herein, hierarchy refers to a system for which the concept of a higher or lower level has meaning. For example, a PCI bus system is hierarchical on several scores. An ordering of levels is observed in that a high level host processor normally communicates from a higher level bus through a bridge to a lower level bus. An ordering of levels is also observed in that buses at equal levels do not communicate directly but through bridges interconnected by a higher level bus. Also, an ordering of levels is observed in that data is filtered by their addresses before being allowed to pass through a bridge, based on the levels involved. Other hierarchical systems exist that may observe an ordering of levels by using one or more of the foregoing concepts, or by using different concepts.
Some personal computers have slots for add-on cards. Because a user often needs additional slots, expansion cards have been designed that will connect between the peripheral bus and an external unit that offers additional slots for add-on cards. For systems for expanding a bus, see U.S. Pat. Nos. 5,006,981; 5,191,657; and 5,335,329. See also U.S. Pat. No. 5,524,252.
For portable computers, special considerations arise when the user wishes to connect additional peripheral devices. Often a user will bring a portable computer to a desktop and connect through a docking station or port replicator to a keyboard, monitor, printer or the like. A user may also wish to connect to a network through a network interface card in the docking station. At times, a user may need additional devices such as hard drives or CD-ROM drives. While technically possible to a limited extent, extending a bus from a portable computer through a cable is difficult because of the large number of wires needed and because of latencies caused by a cable of any significant length.
In U.S. Pat. No. 5,696,949 a host chassis has a PCI to PCI bridge that connects through a cabled bus to another PCI to PCI bridge in an expansion chassis. This system is relatively complicated since two independent bridges communicate over a cabled bus. This cabled bus includes essentially all of the lines normally found in a PCI bus. This approach employs a delay technique to deal with clock latencies associated with the cabled bus. A clock signal generated on the expansion side of the cabled bus: (a) is sent across the cabled bus, but experiences a delay commensurate with the cable length; and (b) is delayed an equivalent amount on the expansion side of the cabled bus by a delay line there, before being used on the expansion side. Such a design complicates the system and limits it to a tuned cable of a pre-designed length, making it difficult to accommodate work spaces with various physical layouts.
U.S. Pat. No. 5,590,377 shows a primary PCI bus in a portable computer being connected to a PCI to PCI bridge in a docking station. When docked, the primary and secondary buses are physically very close. A cable is not used to allow separation between the docking station and the portable computer. With this arrangement, there is no interface circuitry between the primary PCI bus and the docking station. See also U.S. Pat. No. 5,724,529.
U.S. Pat. No. 5,540,597 suggests avoiding additional PCMCIA connectors when connecting a peripheral device to a PC card slot in a portable computer, but does not otherwise disclose any relevant bridging techniques.
U.S. Pat. No. 4,882,702 and show a programmable controller for controlling industrial machines and processes. The system exchanges data serially with a variety of input/output modules. One of these modules may be replaced with an expansion module that can serially communicate with several groups of additional input/output modules. This system is not bridge-like in that the manner of communicating with the expansion module is different than the manner of communicating with the input/output modules. For the expansion module the system changes to a block transfer mode where a group of status bytes are transferred for all the expansion devices. This system is also limited to input/output transactions and does not support a variety of addressable memory transactions. See also U.S. Pat. Nos. 4,413,319; and 4,504,927.
In U.S. Pat. No. 5,572,525 another bus designed for instrumentation (IEEE 488 General Purpose Instrumentation Bus) connects to an extender that breaks the bus information into packets that are sent serially through a transmission cable to another extender. This other extender reconstructs the serial packets into parallel data that is applied to a second instrumentation bus. This extender is an intelligent system operating through a message interpretation layer and several other layers before reaching the parallel to serial conversion layer. Thus this system is unlike a bridge. This system is also limited in the type of transactions that it can perform. See also U.S. Pat. No. 4,959,833.
U.S. Pat. No. 5,325,491 shows a system for interfacing a local bus to a cable with a large number of wires for interfacing with remote peripherals. See also U.S. Pat. Nos. 3,800,097; 4,787,029; 4,961,140; and 5,430,847.
The Small Computer System Interface (SCSI) defines bus standards for a variety of peripheral devices. This CSI bus is part of an intelligent system that responds to high-level commands. Consequently, SCSI systems require software drivers to enable hardware to communicate to the SCSI bus. This fairly complicated system is quite different from bridges such as bridges as specified under the PCI standard. A variety of other complex techniques and protocols exist for transferring data, including Ethernet, Token Ring, TCP/IP, ISDN, FDDI, HIPPI, ATM, Fibre Channel, etc., but these bear little relation to bridge technology.
See also U.S. Pat. Nos. 4,954,949; 5,038,320; 5,111,423; 5,446,869; 5,495,569; 5,497,498; 5,507,002; 5,517,623; 5,530,895; 5,542,055; 5,555,510; 5,572,688; and 5,611,053.
Accordingly, there is a need for an improved system for transferring information between buses.
In accordance with the illustrative embodiments demonstrating features, and advantages of the present invention, there is provided a bridge accessible by a host processor for expanding access over a first bus to a second bus. The first bus and the second bus are each adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The second interface is adapted to couple between the second bus and the link. The first interface and the second interface operating as a single bridge are operable to (a) send outgoing information serially through the link in a format different from that of the first bus and the second bus without waiting for an incoming acknowledgment over said link before inaugurating a transfer of said information over said link, (b) approve an initial exchange between the first bus and the second bus in response to a pending transaction having a characteristic signifying a destination across the bridge, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus, including memory devices and input/output devices that may be present: (i) using on the first bus substantially the same type of addressing as is used to access devices the first bus, and (ii) without first employing a second, intervening one of the bus-compatible devices on the second bus.
In accordance with another aspect of the invention a bridge accessible by a host processor can expand access over a first bus to a second bus. The first bus and the second bus each are adapted to separately connect to respective ones of a plurality of bus-compatible devices. Allowable ones of the devices include memory devices and input/output devices. The bridge has a link, together with a first and a second interface. The first interface is adapted to couple between the first bus and the link. The second interface is adapted to couple between the second bus and the link. The first interface and the second interface are operable to (a) send information serially through the link in a format different from that of the first bus and the second bus, (b) exchange information between the first bus and the second bus according to a predetermined hierarchy giving the first bus a higher level than the second bus, and (c) allow the host processor, communicating through the first bus, to individually address different selectable ones of the bus-compatible devices on the second bus, including memory devices and input/output devices that may be present: (i) using on the first bus substantially the same type of addressing as is used to access devices on the first bus, (ii) without first employing a second intervening one of the bus-compatible devices on the second bus, and (iii) without passing the information through an intervening hierarchical level.
In accordance with another, further aspect of the invention a bridge accessible by a processor can expand access over a first bus to a second bus. The first bus and the second bus each are adapted to separately connect to respective ones of a plurality of bus-compatible devices. The bridge has a link and a first and a second interface. The first interface is coupled between the first bus and the link. The second interface is adapted to couple between the second bus and the link. The first interface and the second interface operate as a single bridge and is operable to transfer information serially through the link in a format different from that of the first bus and the second bus without waiting for an incoming acknowledgment over the link before inaugurating a transfer of the information over the link.
By employing apparatus and methods of the foregoing type, an improved system is achieved for transferring information between buses. In one preferred embodiment, two buses communicate over a duplex link formed with a pair of simplex links, each employing twisted pair or twin axial lines (depending on the desired speed and the anticipated transmission distance). Information from the buses are first loaded onto FIFO (first-in first-out) registers before being serialized into frames for transmission over the link. Received frames are deserialized and loaded into FIFO registers before being placed onto the destination bus. Preferably, interrupts, error signals, and status signals are sent along the link.
In this preferred embodiment, address and data are taken from a bus one transaction at a time, together with four bits that act either as control or byte enable signals. Two or more additional bits may be added to tag each transaction as either: an addressing cycle; acknowledgment of a non-posted write; data burst; end of data burst (or single cycle). If these transactions are posted writes they can be rapidly stored in a FIFO register before being encoded into a number of frames that are sent serially over a link. When pre-fetched reads are allowed, the FIFO register can store pre-fetched data in case the initiator requests it. For single cycle writes or other transactions that must await a response, the bridge can immediately signal the initiator to wait, even before the request is passed to the target.
In a preferred embodiment, one or more of the buses follows the PCI or PCMCIA bus standard (although other bus standards can be used instead). The preferred apparatus then operates as a bridge with a configuration register that is loaded with information specified un er the PCI standard. The apparatus can transfer information between buses depending upon whether the pending addresses fall within a range embraced by the configuration registers. This scheme works with devices on the other side of the bridge, which can be given unique base addresses to avoid addressing conflicts.
In one highly preferred embodiment, the apparatus maybe formed as two separate application-specific integrated circuits (ASIC) joined by a cable. Preferably, these two integrated circuits have the same structure, but can act in two different modes in response to a control signal applied to one of its pins. Working with hierarchical buses (primary and secondary buses) these integrated circuits will be placed in a mode appropriate for its associated bus. The ASIC associated with the secondary bus preferably has an arbiter that can grant masters control of the secondary bus. This preferred ASIC can also supply a number of ports to support a mouse an keyboard, as well as parallel and serial ports.
When used with a portable computer, one of the ASIC""s can be assembled with a connector in a package designed to fit into a PC card slot following the PCMCIA standard. This ASIC can connect through a cable to the other ASIC, which can be located in a docking station. Accordingly, the apparatus can act as a bridge between a CardBus and a PCI bus located in a docking station. Since the preferred ASIC can also provide a port for a mouse and keyboard, this design is especially useful for a docking station. Also, the secondary PCI bus implemented by the ASIC can connect to a video card or to a video processing circuit on the main dock circuit board in order to drive a monitor.
In some embodiments, one ASIC will be mounted in the portable computer by the original equipment manufacturer (OEM). This portable computer will have a special connector dedicated to the cable that connects to the docking station with the mating ASIC. For such embodiments, the existence within the preferred ASIC of ports for various devices can be highly advantageous. An OEM can use this already existing feature of the ASIC and thereby eliminate circuitry that would otherwise have been needed to implement such ports.